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CY62126EV30 mobl ? 1-mbit (64 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05486 rev. *i revised may 31, 2011 1-mbit (64 k 16) static ram features high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c ? automotive: ?40 c to +125 c wide voltage range: 2.2 v to 3.6 v pin compatible with cy62126dv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 4 ? a ultra low active power ? typical active current: 1.3 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power offered in pb-free 48-ball very fine-pitch ball grid array (vfbga) and 44-pin thin small outline package (tsop) ii packages functional description the CY62126EV30 is a high performance cmos static ram organized as 64k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ?? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. placing the device in standby mode reduces power consumption by more than 99 percent when deselected ( ce high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected ( ce high), the outputs are disabled ( oe high), both byte high enable and byte low enable are disabled ( bhe, ble high) or during a write operation ( ce low and we low). to write to the device, take chip enable ( ce) and write enable ( we) inputs low. if byte low enable ( ble) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable ( bhe) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 15 ). to read from the device, take chip enable ( ce) and output enable ( oe) low while forcing the write enable ( we) high. if byte low enable ( ble) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable ( bhe) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. logic block diagram 64k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we bhe a 0 a 1 a 9 a 10 ble [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 2 of 18 contents pin configuration .............................................................3 product portfolio ..............................................................3 maximum ratings .............................................................4 operating range ...............................................................4 electrical characteristics .................................................4 capacitance ......................................................................5 thermal resistance ..........................................................5 data retention characteristics .......................................6 switching characteristics ................................................7 switching waveforms ......................................................8 read cycle no. 1 (address transition controlled) .......8 read cycle no. 2 (oe controlled) ...............................8 write cycle no. 1 (we controlled) ...............................9 write cycle no. 2 (ce controlled) ...............................9 write cycle no. 3 (we controlled, oe low .............10 write cycle no. 4 (bhe/ble controlled, oe low) .......................................10 truth table ......................................................................11 ordering information ......................................................12 ordering code definitions .........................................12 package diagrams ..........................................................13 acronyms ........................................................................15 document conventions .................................................15 units of measure .......................................................15 document history page .................................................16 sales, solutions, and legal information ......................18 worldwide sales and design support .......................18 products ....................................................................18 psoc solutions .........................................................18 [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 3 of 18 pin configuration figure 1. 48-ball vfbga (top view) figure 2. 44-pin tsop ii (top view) [1] product portfolio product range v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max CY62126EV30ll industrial 2.2 3.0 3.6 45 1.3 2 11 16 1 4 CY62126EV30ll automotive 2.2 3.0 3.6 55 1.3 4 11 35 1 30 we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc nc a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h nc nc v cc 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 nc notes 1. nc pins are not connected on the die. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 4 of 18 maximum ratings exceeding maximum ratings may shorten the battery life of the device. these user guidelines are not tested. storage temperature ................................ ?65 c to +150 c ambient temperature with power applied .......................................... ?55 c to +125 c supply voltage to ground potential .............................?0.3 v to 3.6 v (v ccmax + 0.3 v) dc voltage applied to outputs in high z state [3, 4] ..............?0.3 v to 3.6 v (v ccmax + 0.3 v) dc input voltage [3, 4] ???????????? 0.3 v to 3.6 v (v ccmax + 0.3 v) output current into outputs (low) ..............................20 ma static discharge voltage ......................................... > 2001 v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [5] CY62126EV30ll industrial ?40 c to +85 c 2.2 v to 3.6 v automotive ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions 45 ns (industrial) 55 ns (automotive) unit min typ [6] max min typ [6] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 ? 0.4 v i ol = 2.1 ma, v cc > 2.70 v ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 1.8 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 2.2 ? v cc + 0.3 v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ?4 ? +4 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?4 ? +4 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels ? 11 16 ? 11 35 ma f = 1 mhz ? 1.3 2.0 ? 1.3 4.0 i sb1 [7] automatic ce power down current ?cmos inputs ce > v cc ?? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 ( oe, bhe, ble and we), v cc = 3.60 v ?14?135 ? a i sb2 [7] automatic ce power down current ?cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?14?130 ? a notes 3. v il(min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 7. chip enable ( ce) needs to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 5 of 18 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 48-ball vfbga package 44-pin tsop ii package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 4.25 1.125 inch, two-layer printed circuit board 58.85 28.2 c/w ? jc thermal resistance (junction to case) 17.01 3.4 c/w figure 3. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thvenin equivalent all input pulses r th r1 parameters 2.2 v?2.7 v 2.7 v?3.6 v unit r1 16600 1103 ? r2 15400 1554 ? r th 8000 645 ? v th 1.2 1.75 v note 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 6 of 18 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [10] data retention current v cc = v dr , ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v industrial ? ? 3 ? a automotive ? ? 30 ? a t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time CY62126EV30ll-45 45 ? ? ns CY62126EV30ll-55 55 ? ? figure 4. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce notes 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. chip enable ( ce) needs to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or process changes that may affect these parameters. 12. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 7 of 18 switching characteristics over the operating range parameter [13, 14] description 45 ns (industrial) 55 ns (automotive) unit min max min max read cycle t rc read cycle time 45 ? 55 ? ns t aa address to data valid ? 45 ? 55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce low to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [15] 5 ? 5 ? ns t hzoe oe high to high z [15, 16] ? 18 ? 20 ns t lzce ce low to low z [15] 10 ? 10 ? ns t hzce ce high to high z [15, 16] ? 18 ? 20 ns t pu ce low to power up 0 ? 0 ? ns t pd ce high to power down ? 45 ? 55 ns t dbe bhe / ble low to data valid ? 22 ? 25 ns t lzbe bhe / ble low to low z [15] 5 ? 5 ? ns t hzbe bhe / ble high to high z [15, 16] ? 18 ? 20 ns write cycle [17] t wc write cycle time 45 ? 55 ? ns t sce ce low to write end 35 ? 40 ? ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0?0?ns t sa address setup to write start 0?0?ns t pwe we pulse width 35 ? 40 ? ns t bw bhe / ble pulse width 35 ? 40 ? ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0?0?ns t hzwe we low to high z [15, 16] ? 18 ? 20 ns t lzwe we high to low z [15] 10 ? 10 ? ns notes 13. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh and 30-pf load capacitance. 14. ac timing parameters are subject to byte enable signals ( bhe or ble) not switching when chip is disabled. see application note an13842 for further clarification. 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 17. the internal write time of the memory is defined by the overlap of we, ce = v il , bhe, ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must refer to the edge of signal that ter minates write. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 8 of 18 switching waveforms read cycle no. 1 (address transition controlled) [18, 19] read cycle no. 2 ( oe controlled) [19, 20] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe/ ble address notes 18. the device is continuously selected. oe, ce = v il , bhe, ble, or both = v il . 19. we is high for read cycle. 20. address valid before or similar to ce and bhe, ble transition low. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 9 of 18 write cycle no. 1 ( we controlled) [21, 22, 23] write cycle no. 2 ( ce controlled) [21, 22, 23] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 24 t bw t sce data i/o address ce we oe bhe/ ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe/ ble note 24 notes 21. the internal write time of the memory is defined by the overlap of we, ce = v il , bhe, ble or both = v il . all signals must be active to initiate a write and any o f these signals can terminate a write by going inactive. the data input setup and hold timing must refer to the edge of signal th at terminates write. 22. data i/o is high impedance if oe = v ih . 23. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 24. during this period, the i/os are in output state. do not apply input signals. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 10 of 18 write cycle no. 3 ( we controlled, oe low [25] write cycle no. 4 ( bhe/ble controlled, oe low) [25] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 26 ce address we data i/o bhe/ ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 26 data i/o address ce we bhe/ ble notes 25. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period, the i/os are in output state. do not apply input signals. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 11 of 18 truth table ce [27] we oe bhe ble inputs/outputs mode power hxxxx high z deselect/power down standby (i sb ) l x x h h high z output disabled active (i cc ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 27. chip enable must be at cmos levels (not floating). intermediate voltage levels on this pin is not permitted. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 12 of 18 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 CY62126EV30ll-45bvxi 51-85150 48-ball vfbga (pb-free) industrial CY62126EV30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) industrial CY62126EV30ll-45zsxa 51-85087 44-pin tsop ii (pb-free) automotive-a 55 CY62126EV30ll-55bvxe 51-85150 48-ball vfbga (pb-free) automotive-e CY62126EV30ll-55zsxe 51-85087 44-pin tsop ii (pb-free) automotive-e contact your local cypress sales representative for availability of other parts. temperature range: x = i or a or e i = industrial; a = automotive-a; e = automotive-e pb-free package type: xx = bv or zs bv = 48-ball vfbga zs = 44-pin tsop ii speed grade: xx = 45 ns or 55 ns low power voltage: 3 v typical e = process technology 90 nm buswidth = 16 density = 1-mbit family code: mobl sram family company id: cy = cypress cy xx xx 621 2 6 e v30 ll x x - [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 13 of 18 package diagrams figure 5. 48-ball vfbga (6 8 1 mm) bv48/bz48, 51-85150 51-85150 *f [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 14 of 18 figure 6. 44-pin tsop z44-ii, 51-85087 package diagrams (continued) 51-85087 *c [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 15 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable ram random access memory sram static random access memory tsop thin small outline package vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes s micro seconds ma milli amperes mm milli meter ns nano seconds ? ohms % percent pf pico farad v volts w watts [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 16 of 18 document history page document title: CY62126EV30 mobl ? , 1-mbit (64 k 16) static ram document number: 38-05486 rev. ecn no. submission date orig. of change description of change ** 202760 see ecn aju new data sheet *a 300835 see ecn syt converted from advance information to preliminary specified typical standby power in the features section changed e3 ball from dnu to nc in the pin configuration for the fbga package and removed the footnote associated with it on page #2 changed t oha from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively changed t doe , t sd from 15 to 18 ns for 35-ns speed bin changed t hzoe , t hzbe , t hzwe from 12 and 15 ns to 15 and 18 ns for the 35- and 45-ns speed bins, respectively changed t hzce from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed bins, respectively changed t sce ,t bw from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed bins, respectively changed t aw from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respec- tively changed t dbe from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins respectively removed footnote that read ? bhe. ble is the and of both bhe and ble. chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble? on page # 4 removed footnote that read ?if both bhe and ble are toggled together, then t lzbe is 10 ns? on page # 5 added pb-free package information *b 461631 see ecn nxr converted from preliminary to final removed 35 ns speed bin removed ?l? version of CY62126EV30 changed i cc (typ) from 8 ma to 11 ma and i cc (max) from 12 ma to 16 ma for f = f max changed i cc (max) from 1.5 ma to 2.0 ma for f = 1 mhz, i sb1 , i sb2 (max) from 1 ? a to 4 ? a, i sb1 , i sb2 (typ) from 0.5 ? a to 1 ? a, i ccdr (max) from 1.5 ? a to 3 ? a, ac test load capacitance value from 50 pf to 30 pf, t lzoe from 3 to 5 ns, t lzce from 6 to 10 ns, t hzce from 22 to 18 ns, t lzbe from 6 to 5 ns, t pwe from 30 to 35 ns, t sd from 22 to 25 ns, t lzwe from 6 to 10 ns, and updated the ordering information table. *c 925501 see ecn vkn added footnote #7 related to i sb2 and i ccdr added footnote #11 related ac timing parameters *d 1045260 see ecn vkn added automotive information updated ordering information table *e 2631771 01/07/09 nxr/pyrs changed ce condition from x to l in truth table for output disable mode updated template *f 2944332 06/04/2010 vkn added contents removed byte enable from footnote #2 in electrical characteristics added footnote related to chip enable in truth table updated package diagrams updated links in sales, solutions, and legal information *g 2996166 07/29/2010 aju added CY62126EV30ll-45zsxa part in ordering information . added ordering code definitions . modified table footnote format. *h 3113864 12/17/2010 pras updated figure 1 and package diagram, and fixed typo in figure 3.. [+] feedback
CY62126EV30 mobl ? document number: 38-05486 rev. *i page 17 of 18 *i 3270487 05/31/2011 rame updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). updated electrical characteristics . updated data retention characteristics . added acronyms and units of measure . updated in new template. document history page (continued) document title: CY62126EV30 mobl ? , 1-mbit (64 k 16) static ram document number: 38-05486 rev. ecn no. submission date orig. of change description of change [+] feedback
document number: 38-05486 rev. *i revised may 31, 2011 page 18 of 18 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all products and company names mentioned in this document may be the trademarks of their respective holders. CY62126EV30 mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.com/go/automotive clocks & buffers cypress.com/go/clocks interface cypress.com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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